Processor caches are designed to cache data primarily for volatile memory, using a volatile memory namespace. Because the data and the namespace are not generally persistent, processor caches typically destage or flush data to the underlying memory lazily, at an arbitrary time and in an arbitrary order.
In these weakly ordered systems, data can trickle down from a processor cache to the underlying memory with no guarantee of operation order. Without strict ordering of data in operation order, it can be difficult for a memory mapped device to provide data persistence, especially if a host device experiences a power failure or other restart event.